Job Summary

As a Senior Mixed-Signal IC Verification Engineer, you will be using CADENCE simulation tools to verify Integrated Circuits that combine both analog and digital components. Responsibilities include developing verification strategies, creating testbenches, and designing test cases for mixed-signal functionality. You will collaborate closely with analog and digital IC design teams, use simulation tools to ensure accurate performance, and debug issues. Strong expertise in mixed-signal verification methodologies, understanding of analog and digital circuitry, and proficiency in simulation tools are crucial for success in this role.

Key responsibilities

• Work closely with analog and digital teams

• Develop verification plans outlining strategies for testing mixed-signal IC functionality

• Design and implement testbenches to verify analog and digital components of mixed-signal circuits

• Conduct simulations to ensure correct functionality and performance of mixed-signal circuits under various conditions

• Analyze simulation results, identify issues, and collaborate with design teams to resolve them

• Develop and execute verification plans to ensure ICs meet specifications and performance requirements.

• Create and maintain documentation for verification processes, methodologies, and results

• Utilize relevant EDA tools for simulation and verification

• Collaborate with test engineering teams to help transition device from simulation to actual hardware testing

• Provide guidance and mentoring to junior engineers and contribute to improving verification processes

  Requirements

• Bachelor's degree in Electronics Engineering or related subject

• 5 years of experience working in an IC verification and validation environment

• Have worked in verifying designs which have gone into production

• Have a strong understanding of mixed-signal verification principles and current methods

• Solid experience running Mixed Mode Simulations

• Expert in both analog and digital simulation tools (preferably Cadence based)

• Experience in using behavioral models as part of the verification flow

• Familiarity with one of IC modelling languages such as Verilog, SystemVerilog and Verilog-AMS

• Familiarity with scripting languages such as TCL, shell scripts, Python and C is a plus

• Proficient in Microsoft Office applications, especially Word, Excel and PowerPoint

• Have excellent verbal, written and presentation and communication skills

• Comfortable working in a process driven, ISO 9000 framework for new product introduction

• Produce accurate documentation to the highest standards of completeness and precision for presentation

• Stay updated on industry trends, emerging technologies, and advancements in mixed-signal IC design and verification