ASIC/FPGA Design Verification Engineer Location: El Segundo, CA Duration: 6 Months with possible contract to hire/ with possible extension Description: ASIC/FPGA Design Verification Engineer with UVM Experience Create UVM simulation plan from design specification. Create or modify UVC, Score Board, Monitor, and test cases. Verify until functional coverage and code coverage meet project threshold. Document results. Education / Experience: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD, Master+3 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard. Must have min Bachelor’s in Engineering Must have min 5 years of experience UVM experience is important and required. Required Skills: 5+ years of experience 1-2 years of UVM tool Cadence Xcelium verification tool As an equal opportunity employer, ICONMA provides an employment environment that supports and encourages the abilities of all persons without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.